Numerous semiconductor devices can be fabricated together on a semiconductor die. For purposes of illustration, FIG. 1 shows a conventional semiconductor die 10. The conventional semiconductor die 10 includes a substrate 12, a first passivation layer 14 over the substrate 12, a second passivation layer 16 over the first passivation layer 14, a third passivation layer 18 over the second passivation layer 16, and a number of contact pads 20. The boundaries of the substrate 12 are defined by a substrate termination edge 22. The substrate 12 includes an active area 24 in which a number of semiconductor devices (not shown) may be provided, for example, by one or more implanted regions and one or more metallization layers, and a barrier region 26 around the active area 24. The barrier region 26 electrically isolates the active area 24 from the substrate termination edge 22 and thus the surrounding environment. The barrier region 26 is generally provided as an implant that reduces the conductivity of the substrate 12, but can also be an etched mesa or shallow trench isolation (STI). Normally, the barrier region 26 extends from an inside barrier region termination edge 28 to the substrate termination edge 22, forming a barrier around the perimeter of the conventional semiconductor die 10.
The first passivation layer 14 is provided over the active area 24 and extends over the barrier region 26 to a passivation termination edge 30. The second passivation layer 16 is over the first passivation layer 14 and similarly extends to the passivation termination edge 30. The third passivation layer 18 is over the second passivation layer 16 and similarly extends to the passivation termination edge 30. The contact pads 20 may be provided on the second passivation layer 16 and be exposed to the outside environment via one or more openings in the third passivation layer 18. While not shown, metallization layers within the first passivation layer 14 and the second passivation layer 16 may couple the contact pads to one or more semiconductor devices in the active area 24. The passivation termination edge 30 is inset from the substrate termination edge 22 by a certain distance D.
The first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 are provided to isolate the semiconductor devices in the active area 24 from the surrounding environment, both electrically and physically. However, when the conventional semiconductor die 10 is in a humid environment and subject to high temperatures and/or bias voltages, one or more of the first passivation layer 14, the second passivation layer 16, and the third passivation layer 18 may delaminate from their underlying layer, allowing moisture to penetrate into the active area 24. This may cause failure of the conventional semiconductor die 10. This problem is exacerbated by an electric field created by operating one or more semiconductor devices in the active area 24, which may be quite high at the passivation termination edge 30. This electric field may draw moisture from the passivation termination edge 30 towards the active area 24 and thus cause failure of the conventional semiconductor die 10 as discussed above.
In light of the above, there is a need for a semiconductor die with improved ruggedness and methods for manufacturing the same.